1. Field of the Invention
This invention relates to producing an integrated circuit (“IC”) device, particularly with regard to modeling parameters of an electronic sub-component block in the IC device, and particularly with regard to selecting among electrical properties and timing delays for many sub-components in a dynamic design environment in order to ensure accuracy for a top-level timing analysis.
2. Description of Background
In IC's, particularly in complex IC's such as for SMP computers like IBM® zSeries® mainframe computer systems manufactured by IBM, it is common to partition the IC into entities having a logical hierarchy. Many logical entities of the IC are included in a hierarchy of entities that are considered in the timing analysis process. Random logic macros (“RLM's,” also referred to simply as “macros”) are a major one of them. They typically include anywhere from a few hundred to several thousand leaf cells (also referred to as “elements”), such as combinatorial logic gates and latches.
The prior art shown in FIG. 1 illustrates an IC chip 110, including macros 120, which include leaf cells 130. A process of producing an IC chip 110 may include a design process, wherein leaf cells 130, macros 120 and the chip 110 are defined as logical entities in a hierarchical representation of chip 110. In this context, it is necessary to perform a detailed timing analysis at the top-most level of the design and at all sub-level hierarchical boundaries to ensure the machine will function at the desired frequency in order to meet the performance objectives. Numerous processes lead up to timing analysis. One such process, known a “synthesis,” produces logical and physical (placement information) data for all the leaf cells in each RLM. This is done by running a heuristical synthesis tool on a representation of the RLM logic, which is typically a textual representation in the form of VHDL.
Once an RLM is synthesized, which produces a logical and physical representation for all its leaf cells, then the RLM's electrical parameters, like capacitance, resistance and inductance, are modeled at every point in the macro in schematic fashion. In addition, timing data such as gate propagation delay, wire delay, and phase information is also then extracted at every point. A set of output files is produced by each these processes and is referred to as a nominal delay rule (NDR). Any one of these NDR's for each macro can then be used in an overall timing analysis process, which is a process that takes into account a combination of many macros.
Aspects of the above are shown in FIG. 2, which illustrates a series of processes 202, 204, and 206 for designing an IC chip 110 (FIG. 1), according to the prior art. Processes 202, 204, and 206 produce respective NDR's 210, 212 and 214 of corresponding types. That is, as shown in the illustrated instance, synthesizing process 202 receives a logical representation 201 of an RLM MACRO_1 in a VHDL format, which is a text based format, and responsively produces a logical and physical representation 203 and delay based NDR's 210, which are well-known data structures in the form of files for use in timing analysis that represent timing related aspects of logical and physical representation 203. Then, modeling process 204 receives logical and physical representation 203 and responsively produces a schematic electrical representation 205 of MACRCO_1 and also produces schematic based NDR's 212, which, are well-known data structures in the form of files for use in timing analysis that represent, certain timing related, aspects of schematic electrical representation 205. Then, extraction process 206 receives electrical representation 205 and responsively produces a physical electrical representation 207, which includes physical wire and silicon aspects, also responsively produces extraction based NDR's 214, which are well-known data structures in the form of files for use its timing analysis that represent certain timing related aspects of physical electrical representation 207.
As shown in FIG. 2, processes 202, 204, and 206 are, likewise, performed for MACRO_2, MACRO_3, etc., so that they producing corresponding NDR's 210, 212, and 214 for each one of the RLM's MACRO_1, MACRO_2 and MACRO_3. FIG. 2 also illustrates the use of NDR's 210, 212 and 214 in a timing analysis process 250, which produces overall chip 110 level timing results. As previously explained, any one of the NDR's 210, 212 and 214 may be used for each macro as timing analysis 250 input 240. Therefore, selections must occur. As shown, NDR's 214 are selected in all cases according to the illustrated prior art prior art selection process.
FIG. 3 illustrates a prior art NDR selection process 310, which is one of the sub processes in an overall design process for an IC chip 110 (FIG. 1). An RLM NDR library serves as the main input to the NDR selection process 310 that is run at the beginning of the timing analysis. From the library comes three type of NDR's: 1) extraction based 214, 2) schematic based 212, and 3) delay rule based 210. All three types of NDR's often exist for every RLM in the library. In the instance illustrated in FIG. 2, this is the case.
Process 305 locates the NDR's by type. The NDR types enter the selection process 310 by type, as shown, and a determination is made as to which NDR to select for each RLM, based on established rules. The rules are: 1) select extracted NDR 214, if present; 2) if extracted NDR 214 is not present, then select schematic NDR 212, and, finally, 3) if neither extracted NDR 214 nor schematic NDR 212 are present, then default to a delay based NDR 210. The NDR selected for each RLM is used as input 240 to the main timing analysis. All NDR types for a RLM that are not selected are discarded.
Thus, applying process 310 shown in FIG. 3 to the illustrated instance of FIG. 2, since extraction based NDR's 214 exist for RLM MACRO_1, and also exist (although are not explicitly illustrated) for MACRO_2 and MACRO_3, the NDR's selected by process 310 are all NDR's 214, as shown for input 240.
A conventional procedure for selecting the most appropriate NDR for each ELM is to preferably select an NDR that is modeled from extracted data, since that kind of NDR incorporates real wire delays and parasitics, and thus maintains the highest degree of accuracy over all other forms. The next preferred NDR is conventionally one modeled after schematic data, which includes an estimate on she wire delays and parasitics, but still has a high degree of accuracy on the physical placement and delays of the leaf cells in the circuit. The least preferred is conventionally the NDR modeled after delay statements, which include no physical gate placement or wire data at all.